In a typical memory, memory cells are arranged in rows and columns, as shown in FIG. 1. Each memory cell 104 resides within a cell region 102, and each memory cell 104 has a control input coupled to a word line 106, and a data terminal coupled to a bit line 108. All of the memory cells 104 in a row are coupled to the same word line 106, and all of the memory cells 104 in a column are coupled to the same bit line 108.
Also coupled to the bit lines 108 are a precharge circuit 112 and a sensing circuit and latch 114. The precharge circuit 112 precharges each bit line 108 to prepare the bit line for a read operation, and the sensing circuit and latch 114 senses the data on the bit lines 108, and latches/stores it. In effect, the sensing circuit and latch 114 acts as a buffer for the data on the bit lines 108.
In a typical read operation, the memory 100 functions as follows. Initially, the precharge circuit 112 precharges the bit lines 108 to prepare them for the read operation. Then, the decoder 110 receives a read enable signal and a set of address signals on the address lines. In response, the decoder 110 decodes the address, and activates one of the word lines 106 (the precharge circuit 112 stops precharging the bit lines 108 prior to the activation of the word line 106). As a result of the word line 106 being activated, each of the memory cells 104 coupled to that word line 106 outputs its data onto a corresponding bit line 108. Depending upon the data stored therein, each memory cell 104 may leave its corresponding bit line 108 charged, or it may discharge the bit line 108. The sensing circuit and latch 114 senses the charge on each bit line 108 and determines therefrom the data on each bit line 108. The latch 114 then latches and stores that data. At some point, towards the end of the word line being activated, the sensing circuit and latch 114 completes its latching operation and the sensing circuit 114 is turned off. After that happens, the precharge circuit 112 is turned on again to precharge the bit lines 108. In this manner, a read cycle is completed.
In the memory 100 of FIG. 1, there are X bit lines 108 (hence, the memory 100 is able to read out X bits at a time) and Y word lines 106. With this number of bit lines 108 and word lines 106, the memory 100 can accommodate an X times Y number of memory cells 104. In the memory industry, there is a constant push to increase the density of memories. With the size of a cell region 102 limited to a certain size by practical considerations, there is a limit to which the density of the memory 100 in FIG. 1 can be increased. To increase the memory density beyond this limit, a different memory architecture needs to be used.